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The setup of the configuration jumpers on the SHB is described below.
* indicates the default value of each jumper.
NOTE:
For two-position jumpers (3-post), "RIGHT" is toward the bracket end of the board; "LEFT" is toward the processor(s).
Install for one power-up cycle to reset the password to the default (null password).
Remove for normal operation. *
The Flash ROM has two programmable sections:
the Boot Block for "flashing" in the BIOS and the Main Block for the executable BIOS and PnP parameters. Normally only the Main Block is updated when a new BIOS is flashed into the system.
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JU10 |
JU11 |
All Blocks Write Enabled Boot Block Write Protected Block 2-16 Write Protected |
Remove * Install Remove |
Remove * Remove Install |
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Install on the RIGHT to operate.*
Install on the LEFT to clear.
NOTE:
To clear the CMOS, power down the system and
install the jumper on the LEFT. Wait for at least two
seconds, move the jumper back to the RIGHT and turn the
power on. When AMIBIOS displays the "CMOS Settings
Wrong" message, press F1 to go into the BIOS Setup
Utility, where you may reenter your desired BIOS settings,
load optimal defaults or load failsafe defaults.
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Pin 1 on the connectors is indicated by the square pad on the PCB.
3 pin single row header, Molex #22-23-2031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
+12V |
| 3 |
FanTach |
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4 pin single row header, Amp #640456-4
| PIN |
SIGNAL |
| 1 |
Speaker Data |
| 2 |
Key |
| 3 |
Gnd |
| 4 |
+5V |
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2 pin single row header, Amp #640456-2
| PIN |
SIGNAL |
| 1 |
External Reset In (Low Active) |
| 2 |
Gnd |
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40 pin dual row header, Amp #1-1761610-3
| PIN |
SIGNAL |
| 1 |
Reset |
| 3 |
Data 7 |
| 5 |
Data 6 |
| 7 |
Data 5 |
| 9 |
Data 4 |
| 11 |
Data 3 |
| 13 |
Data 2 |
| 15 |
Data 1 |
| 17 |
Data 0 |
| 19 |
Gnd |
| 21 |
DRQ 0 |
| 23 |
IOW |
| 25 |
IOR |
| 27 |
IORDY |
| 29 |
DACK 0 |
| 31 |
IRQ 14 |
| 33 |
Add 1 |
| 35 |
Add 0 |
| 37 |
CS 1P |
| 39 |
IDEACTP |
|
| PIN |
SIGNAL |
| 2 |
Gnd |
| 4 |
Data 8 |
| 6 |
Data 9 |
| 8 |
Data 10 |
| 10 |
Data 11 |
| 12 |
Data 12 |
| 14 |
Data 13 |
| 16 |
Data 14 |
| 18 |
Data 15 |
| 20 |
NC |
| 22 |
Gnd |
| 24 |
Gnd |
| 26 |
Gnd |
| 28 |
SELPDP |
| 30 |
Gnd |
| 32 |
NC |
| 34 |
PCBL DET* |
| 36 |
Add 2 |
| 38 |
CS 3P |
| 40 |
Gnd |
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* For ATA/66 and ATA/100 drives, which should be set
for Cable Select for proper speed operation. If other
Drives are detected, pin definition is Gnd.
4 pin single row header, Amp #640456-4
| PIN |
SIGNAL |
| 1 |
LED + |
| 2 |
LED - |
| 3 |
LED - |
| 4 |
LED + |
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15 pin HD15 connector, Kycon #K31X-E15S-N
| PIN |
SIGNAL |
| 1 |
Red |
| 2 |
Green |
| 3 |
Blue |
| 4 |
NC |
| 5 |
Gnd |
|
| PIN |
SIGNAL |
| 6 |
Gnd |
| 7 |
Gnd |
| 8 |
Gnd |
| 9 |
+5V |
| 10 |
Gnd |
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| PIN |
SIGNAL |
| 11 |
NC |
| 12 |
EEDI |
| 13 |
HSYNC |
| 14 |
VSYNC |
| 15 |
EECS |
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Dual RJ-45 connector, Pulse #JG0-0024NL
Each individual RJ-45 connector is defined as follows:
| PIN |
SIGNAL |
| 1 |
TRP1+ |
| 2 |
TRP1- |
| 3 |
TRP2+ |
| 4 |
TRP3+ |
| 5 |
TRP3- |
| 6 |
TRP2- |
| 7 |
TRP4+ |
| 8 |
TRP4- |
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8 pin dual row header, Molex #702-46-08-01
(+5V fused with self-resetting fuses)
| PIN |
SIGNAL |
| 1 |
+5V - USB2 |
| 3 |
USB2- |
| 5 |
USB2+ |
| 7 |
Gnd - USB2 |
|
| PIN |
SIGNAL |
| 2 |
+5V - USB3 |
| 4 |
USB3- |
| 6 |
USB3+ |
| 8 |
Gnd - USB3 |
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USB vertical connector, Molex #47500-0001
(+5V fused with self-resetting fuse)
| PIN |
SIGNAL |
| 1 |
+5V - USB0 |
| 2 |
USB0- |
| 3 |
USB0+ |
| 4 |
Gnd - USB0 |
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USB vertical connector, Molex #47500-0001
(+5V fused with self-resetting fuses)
| PIN |
SIGNAL |
| 1 |
+5V - USB1 |
| 2 |
USB1- |
| 3 |
USB1+ |
| 4 |
Gnd - USB1 |
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3 pin single row header, Molex #22-23-2031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
+12V |
| 3 |
Fan Tach |
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76 pin controlled impedance connector, Samtec #MIS-038-01-FD-K
| PIN |
SIGNAL |
| 1 |
+12V |
| 3 |
NC |
| 5 |
NC |
| 7 |
NC |
| 9 |
NC |
| 11 |
NC |
| 13 |
ICH_SMI# |
| 15 |
ICH_SIOPME# |
| 17 |
Gnd |
| 19 |
L_FRAME# |
| 21 |
L_DRQ1# |
| 23 |
L_DRQ0# |
| 25 |
SERIRQ |
| 27 |
Gnd |
| 29 |
PCLK14SIO |
| 31 |
Gnd |
| 33 |
SMBDATA_RESUME |
| 35 |
SMBCLK_RESUME |
| 37 |
SALRT#_RESUME |
| 39 |
Gnd |
| 41 |
EXP_CLK100 |
| 43 |
EXP_CLK100# |
| 45 |
Gnd |
| 47 |
C_PE_TXP4 |
| 49 |
C_PE_TXN4 |
| 51 |
Gnd |
| 53 |
C_PE_TXP3 |
| 55 |
C_PE_TXN3 |
| 57 |
Gnd |
| 59 |
C_PE_TXP2 |
| 61 |
C_PE_TXN2 |
| 63 |
Gnd |
| 65 |
C_PE_TXP1 |
| 67 |
C_PE_TXN1 |
| 69 |
Gnd |
| 71 |
+3.3V |
| 73 |
+3.3V |
| 75 |
+3.3V |
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| PIN |
SIGNAL |
| 2 |
+5V_STANDBY |
| 4 |
+5V_STANDBY |
| 6 |
+5V_DUAL |
| 8 |
+5V_DUAL |
| 10 |
NC |
| 12 |
NC |
| 14 |
ICH_RCIN# |
| 16 |
ICH_A20GATE |
| 18 |
Gnd |
| 20 |
L_AD3 |
| 22 |
L_AD2 |
| 24 |
L_AD1 |
| 26 |
L_AD0 |
| 28 |
Gnd |
| 30 |
PCLK33LPC |
| 32 |
Gnd |
| 34 |
IPMB_DAT |
| 36 |
IPMB_CLK |
| 38 |
IPMB_ALRT# |
| 40 |
Gnd |
| 42 |
EXP_RESET# |
| 44 |
ICH_WAKE# |
| 46 |
Gnd |
| 48 |
C_PE_RXP4 |
| 50 |
C_PE_RXN4 |
| 52 |
Gnd |
| 54 |
C_PE_RXP3 |
| 56 |
C_PE_RXN3 |
| 58 |
Gnd |
| 60 |
C_PE_RXP2 |
| 62 |
C_PE_RXN2 |
| 64 |
Gnd |
| 66 |
C_PE_RXP1 |
| 68 |
C_PE_RXN1 |
| 70 |
Gnd |
| 72 |
+5V |
| 74 |
+5V |
| 76 |
+5V |
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2 pin single row header, Amp #640456-2
| PIN |
SIGNAL |
| 1 |
LED - |
| 2 |
LED + |
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7 pin vertical connector, Molex #67491-0031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
TX+ |
| 3 |
TX- |
| 4 |
Gnd |
|
| PIN |
SIGNAL |
| 5 |
RX- |
| 6 |
RX+ |
| 7 |
Gnd |
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7 pin vertical connector, Molex #67491-0031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
TX+ |
| 3 |
TX- |
| 4 |
Gnd |
|
| PIN |
SIGNAL |
| 5 |
RX- |
| 6 |
RX+ |
| 7 |
Gnd |
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7 pin vertical connector, Molex #67491-0031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
TX+ |
| 3 |
TX- |
| 4 |
Gnd |
|
| PIN |
SIGNAL |
| 5 |
RX- |
| 6 |
RX+ |
| 7 |
Gnd |
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7 pin vertical connector, Molex #67491-0031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
TX+ |
| 3 |
TX- |
| 4 |
Gnd |
|
| PIN |
SIGNAL |
| 5 |
RX- |
| 6 |
RX+ |
| 7 |
Gnd |
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3 pin single row header, Molex #22-23-2031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
+12V |
| 3 |
FanTach |
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7 pin vertical connector, Molex #67491-0031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
TX+ |
| 3 |
TX- |
| 4 |
Gnd |
|
| PIN |
SIGNAL |
| 5 |
RX- |
| 6 |
RX+ |
| 7 |
Gnd |
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7 pin vertical connector, Molex #67491-0031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
TX+ |
| 3 |
TX- |
| 4 |
Gnd |
|
| PIN |
SIGNAL |
| 5 |
RX- |
| 6 |
RX+ |
| 7 |
Gnd |
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The four-channel Double Data Rate (DDR2) memory interface on the MCXT and MCXI SHBs supports up to 16GB of Fully Buffered DIMM (FB-DIMM) memory; the MCXT-E and MCXI-E models support up to 32GB of FB-DIMM memory.
FB-DIMMs have "Advanced Memory Buffer" chips that provide enhanced signal integrity and improved error detection that help reduce soft memory errors. FB-DIMM memory technology improves overall system reliability by extending the current ECC capability to include protection of command and address data. FD-DIMMs feature automatic retries when a memory error is detected, which results in uninterrupted system operation in the event of transient errors.
An MCX-series SHB uses industry standard 72-bit wide ECC gold finger FB-DIMM memory modules in four (MCXT/MCXI) or eight (MCXT-E/MCXI-E) 240-pin sockets. The FB-DIMMs must be PC2-4200 or PC2-5300 (DDR2-533 or DDR2-667) and comply with the JEDEC Rev. 2.0 specifications.
The following dual-rank FB-DIMM sizes are supported:
| FB-DIMM Size |
DIMM Type |
ECC |
| 512MB |
Registered |
64M x 72 |
| 1GB |
Registered |
128M x 72 |
| 2GB |
Registered |
256M x 72 |
| 4GB |
Registered |
512M x 72 |
A minimum of one 512MB FB-DIMM is required and must be populated in DIMM socket BK0A.
With the bracket end of the board to the right, the four FB-DIMM sockets available on the MCXT and MCXI SHBs are numbered BK0A, BK1A, BK0B and BK1B, from top to bottom. On the extended-memory MCXT-E and MCXI-E SHBs, there are an additional four FB-DIMM sockets. The upper sockets are BK2A and BK2B, from left to right, and the lower sockets are BK3A and BK3B. These socket definitions are illustrated in the board layouts. All memory modules must have gold contacts.
To maximize memory interface speed and bandwidth, and to take full advantage of the four-channel memory interface of the SHB's memory controller hub, the FB-DIMMs in socket banks 0A and 1A must be identical with respect to manufacturing, speed, timing and organization. Likewise, FB-DIMMs used in sockets 0B and 1B must be identical. FB-DIMMs in socket banks contained within the same memory channel, i.e., 0A and 2A do not have to be identical.
A minimum of one 512MB FB-DIMM is required and must be populated in DIMM socket BK0A. When using more that one FB-DIMM, you must populate the memory sockets in multiples of two in order to maximize the speed and performance of the memory interface. The following table explains the DDR2 FB-DIMM population rules:
FB-DIMM POPULATION CONFIGURATION |
FB-DIMM Sockets (MCXT, MCXE) |
FB-DIMM Sockets (MCXT-E, MCXI-E) |
| BANK 0A |
BANK 1A |
BANK 0B |
BANK 1B |
BANK 2A |
BANK 2B |
BANK 3A |
BANK 3B |
| Single Module |
FB-DIMM |
Empty |
Empty |
Empty |
Empty |
Empty |
Empty |
Empty |
| Two Modules |
FB-DIMM |
FB-DIMM |
Empty |
Empty |
Empty |
Empty |
Empty |
Empty |
| Four Modules |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
Empty |
Empty |
Empty |
Empty |
| Six Modules |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
Empty |
Empty |
| Eight Module |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
FB-DIMM |
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MCX Series (6633-, 6638-, 6685-, 6700-xxx) Product Detail.
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